1. Field of the Invention
This invention relates generally to a method of defect classification in a semiconductor manufacturing testing system. More specifically, this invention relates to a method of defect classification in a semiconductor manufacturing testing system in which a scanning tool that uses parametric defect data to provide a thumbprint of each defect and the defects are placed in "bins" according to the thumbprints.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects during the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, chips that must be discarded because of a defect or defects increases the cost of the remaining usable chips.
A single semiconductor chip can require numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits.
Although it would be desirable to be able to identify and analyze each defect on each wafer in every manufacturing run, it is not practical. In practice, a particular lot (a number of wafers) is selected to be representative of the manufacturing run. A single wafer or multiple wafers is then selected from the lot to be analyzed. Because of the number of processes, it may not be possible to reanalyze each wafer after each process. Therefore, only certain processes are analyzed. The wafer is placed in an inspection tool that identifies defects after each process that is to be analyzed. The inspection tool scans the wafer and detects the defects on the wafer. As the tool detects each defect, the tool measures certain parameters that are descriptive of the defect. These parameters consist of 80 or more characteristics, such as estimated size, polarity, intensity, color, brightness, and roundness. This data is for the most part unused. After the complete wafer is scanned, a wafer classifier inspects a random sample of the defects and assigns a classification code to each defect. These classifications are charted into a Pareto Chart format that gives an indication of the total defect distribution across the wafer. However, this method is inherently inaccurate for two reasons, the random nature of the selection of the defects to analyze and the small sample size chosen for classification.
Therefore, what is needed is a method to improve the extrapolated accuracy of the defect distribution across the entire wafer.